Rapid Design Exploration of Low Pass Highly Efficient Single Loop Single Bit Sigma Delta (Σ∆) Modulators

S. Vamsee Krishna; P. Sudhakara Reddy; S. Chandra Mohan Reddy

doi:10.24423/cames.511

S. Vamsee Krishna Jawaharlal Nehru Technological University Anantapuramu
P. Sudhakara Reddy Srikalahastweeswara Institute of Technology
S. Chandra Mohan Reddy Jawaharlal Nehru Technological University Ananthapuramu

DOI: http://dx.doi.org/10.24423/cames.511

Abstract

A rapid design and verification of sigma delta modulators are presented at the system level with high accuracy and computational efficiency. Sigma delta analog to digital converters showcased an excellent choice for low bandwidth applications from near DC to high bandwidth standard 5G applications. The conceptualization of the graphical user interface (GUI) in the efficient selection of integrator weights has been proposed, which solves various tradeoffs between various abstraction levels. The sigma delta modulator of the 5th order is designed and simulated using the proposed design methodology of calculating integrator weights for targeted specifications. The efficiency of design exploration and optimum selection of integrator coefficients has been investigated on single loop architectures. Power and performance of the selected modulator has been verified in the time domain behavioral simulation. The discrete time circuit technique has been adopted for design of distributed feedback, feed forward architectures and comparison of performance metrics done between selected architectures. A huge design space is computed for the best design parameters that offers ultra-low power and high performance. The proposed virtual instruments supported the methodology for designing delta sigma modulators at the system level achieving SNDR of 122 dB over a bandwidth of 5 kHz at a clock frequency of 1 MHz.

Keywords

sigma delta modulator, single loop, time domain, virtual instruments, biomedical applications,

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